昨兒個讀了《Write Greate Code》Volume1: Understanding the Machine
想通了很久困惑的問題，受益匪淺，貼圖以共享

1. 約翰.馮.諾伊曼體系結(jié)構(gòu)(Von Neumann Architecture，VNA)

2.內(nèi)存物理組織
Read

Write

3.地址總線
8bit

16bit
Say more here, there are a concept named bank which confused me when I read <Intel Architecture Software Developer's Manual>. The?physical memory is organized into two banks, even and odd, in 16 bits data addr bus.
So, 16 bits x86 CPUs always put even addr on the addr bus, and if they access odd addr, the CPUs must op memory twice.?

32bits
As with 16 bits, 32bits x86 CPUs always put 4X addr on?their addr bus.?

4. Byte Genders
Little Endian


Big Endian

5.?System Clock

6.?內(nèi)存訪問
內(nèi)存訪問時間：從CPU講地址放到地址總線上開始到CPU從數(shù)據(jù)總線上取得數(shù)據(jù)之間的時間。
x86 CPU，具有單周期內(nèi)存訪問時間

等待狀態(tài)——(CPU)別跑那么快，等等我(IO)

Cache-引用的時空局部特性(temporal and spatial locality of reference)



7.?內(nèi)存尋址模式
直接(direct), 間接(indirect),?變址(indexed),?比例變址(scaled indexed)

8.?內(nèi)存層次結(jié)構(gòu)(hierarchy)
說一下NUMA，非一致內(nèi)存訪問(Non-Uniform Memory Access)，NUMA本來是說不同類型的內(nèi)存有著不同的訪問時間，此處用來描述一些電氣上與主存類似，但由于其速度比主存低很多的內(nèi)存。一如，顯存，閃存。

So...,?that's all for today :p
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