0x0

前些天組里老司機@梁希在jvm的項目榨干機器性能之余，為了檢查下gcc編譯器和Intel Xoen CPU的正確性，寫了一組測試代碼測試了下mfence指令的效果

`
mfence Opcode : 0F AE /6

Performs a serializing operation on all load-from-memory and store-to-memory instructions that were issued prior the MFENCE instruction. This serializing operation guarantees that every load and store instruction that precedes in program order the MFENCE instruction is globally visible before any load or store instruction that follows the MFENCE instruction is globally visible. The MFENCE instruction is ordered with respect to all load and store instructions, other MFENCE instructions, any SFENCE and LFENCE instructions, and any serializing instructions (such as the CPUID instruction).
Weakly ordered memory types can be used to achieve higher processor performance through such techniques as out-of-order issue, speculative reads, write-combining, and write-collapsing.
The degree to which a consumer of data recognizes or knows that the data is weakly ordered varies among applications and may be unknown to the producer of this data. The MFENCE instruction provides a performance-efficient way of ensuring load and store ordering between routines that produce weakly-ordered results and routines that consume that data.
It should be noted that processors are free to speculatively fetch and cache data from system memory regions that are assigned a memory-type that permits speculative reads (that is, the WB, WC, and WT memory types). The PREFETCHh instruction is considered a hint to this speculative behavior. Because this speculative fetching can occur at any time and is not tied to instruction execution, the MFENCE instruction is not ordered with respect to PREFETCHh instructions or any other speculative fetching mechanism (that is, data could be speculatively loaded into the cache just before, during, or after the execution of an MFENCE instruction).
`

簡單來說就是一個可以在CPU亂序執(zhí)行中保證真實的load/store順序的指令

0x1
老司機寫了一個小程序(注：有誤版)
// file: order.c

大概邏輯是： 一共有3個變量，v1.i, v2.i, b ,起了2個線程，一個順序?qū)懭雟1和v2，一個讀v1和v2，互相通過改變b的值來通訊，然后兩個線程不停循環(huán)。

這個程序會掛在
printf("assert error, cnt = %d, icnt = %d, i1 = %d, i2 = %d\n", cnt, icnt, i1, i2); 
這條斷言上，意思是線程1在順序?qū)懭雟1和v2，但是主線程卻出現(xiàn)讀到 v1=0，v2=1的情況。

0x2

然后我?guī)兔θタ戳艘幌拢X得這種寫法甚是粗暴，于是原樣照搬了一個c++11版:

因為是原樣照搬，所以肯定還是會掛，但是畢竟語義上更好理解了

我們先來分析一下為什么會掛

• 線程1對于v1，v2的寫入順序一定是一致的
• Memory Barrier也保證了他們寫入順序?qū)ζ渌€程的可見性（很有迷惑性的一點）
• 但是主線程卻可以讀到 v1=0,v2=1的情況
• 所以情況就是雖然順序?qū)懭肓耍莿e的線程沒有看到正確的順序？
• Intel: 并不是！
• 原因是搞錯了因果關(guān)系，他真正保證的順序是當你讀到v2的new value的時候，那么v1也一定被寫入了。
• 解決方案就是互換上面代碼中我用**星號**標注出的兩行
• done

在舊寫法中，掛掉的情況是線程1寫入v1 = 1，主線程讀v1，沒有讀到，那么主線程認為v1是0，然后線程1繼續(xù)寫入v2，主線程讀到了，主線程認為v2是1。 然后掛在了斷言上。

兩行互換后，主線程首先讀取v2，如果v2已經(jīng)是1了，那么v1也一定是1，反之亦然。

0x3

當然，想讓跑通那個例子不需要那么多的atomic<>，精簡之后利用c++11的memory_order可以寫成如下：

利用變量b在兩個線程之間同步，如下圖

 (Thead 1)

   v1.i = 1;
   v2.i = 1;
   
   b.store(0, memory_order_release) <---+
                                                             |
                                                synchronize with b
                                                 (happend before)
                                                             |
                                                            +----->  b.load(memory_order_acquire)
                                                                          
                                                                        i1 = v1.i
                                                                        i2 = v2.i

                                                                       (Thread 2)

我們查看下生成的代碼
g++ -std=c++11 -pthread -g -O2 order.cpp

 v1.i = 1;
  400be6:       c7 05 d0 10 20 00 01    movl   $0x1,0x2010d0(%rip)        # 601cc0 <v1>
  400bed:       00 00 00 
        v2.i = 1;
  400bf0:       c7 05 86 10 20 00 01    movl   $0x1,0x201086(%rip)        # 601c80 <v2>
  400bf7:       00 00 00 
        memory_order __b = __m & __memory_order_mask;
        __glibcxx_assert(__b != memory_order_acquire);
        __glibcxx_assert(__b != memory_order_acq_rel);
        __glibcxx_assert(__b != memory_order_consume);

        __atomic_store_n(&_M_i, __i, __m);
  400bfa:       c7 05 5c 10 20 00 00    movl   $0x0,0x20105c(%rip)        # 601c60 <b>
  400c01:       00 00 00 
        b.store(0, memory_order_release);

  

  400a58:       8b 05 02 12 20 00       mov    0x201202(%rip),%eax        # 601c60 <b>
            int b2 = b.load(memory_order_consume);
            if (b2 != 0) {
  400a5e:       85 c0                   test   %eax,%eax
  400a60:       75 f3                   jne    400a55 <main+0x55>
                continue; 
            }
            int i1 = v1.i;
  400a62:       8b 0d 58 12 20 00       mov    0x201258(%rip),%ecx        # 601cc0 <v1>
            int i2 = v2.i;
  400a68:       44 8b 05 11 12 20 00    mov    0x201211(%rip),%r8d        # 601c80 <v2>

看來Intel的Strong Memory Model已經(jīng)保證了這一點，Memory Barrier都不需要了

（雖然標題里面有MemoryBarrier，但是內(nèi)容里面根本沒涉及的樣子。。）