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1-15 通過JTAG調(diào)試板子，通過串口或USB引導(dǎo)加載操作系統(tǒng)
Table 3-7. AIPI1 Memory Map
0x1000 A000 – 0x1000 AFFF UART1 4 Kbyte
0x1002 4000 – 0x1002 4FFF USB OTG 4 Kbyte
0x1002 5000 – 0x1002 5FFF USB OTG 4 Kbyte
Table 7-20. Reset Module Pin and Signal Descriptions
HRESET：Hard Reset—An active low signal that resets the ARM9 Platform. This signal is deasserted during the low phase of HCLK. This signal also appears on the RESET_OUT pin of the i.MX21.
7.4.2 ARM9 Platform Reset
Any qualified global reset signal resets the ARM9 platform and all related peripherals to their default state. After the internal reset is deasserted, the ARM9 processor begins fetching code from the internal bootstrap ROM or CS0 space. The memory location of the fetch depends on the configuration of the BOOT pins and the value of the TEST pin on the rising edge of the HRESET.
7-32 系統(tǒng)從片選信號(hào)CS0對(duì)應(yīng)存儲(chǔ)區(qū)域或者是從iROM啟動(dòng)，這取決于BOOT[3:0]的設(shè)置和處于HRESET上升沿時(shí)TEST pin的值。
9.2 System Boot Mode Selection
If the fuse of the BOOT_INT is blown（表9-2中Blown = Internal=1？）, the BOOT Address will be generated based on the BOOT[3:0] information.
Silicon ID Register的BOOT_INT位=0時(shí)，從由BOOT[3:0]所決定的外部存儲(chǔ)空間啟動(dòng)；
Silicon ID Register的BOOT_INT位=1時(shí)，從0x0處啟動(dòng)。
The BOOT pins must not change once the i.MX21 is out of reset. For proper operation, BOOT[3] must always be tied to VSS.
表9-19給出了設(shè)置BOOT[3:0]所對(duì)應(yīng)的各種啟動(dòng)模式以及初始地址
BOOT[3:0]決定了映射到0x0的外部存儲(chǔ)地址，即Reset Vector的值。
處理器啟動(dòng)順序由SIDR和BOOT[3:0]的配置決定，默認(rèn)BOOT_INT位=0時(shí)，即從由BOOT[3:0]所決定的外部存儲(chǔ)空間啟動(dòng)。
10.5.1.1 Wafer Test
By default, the silicon is configured to bootup externally and all security related modules are disabled via the default laser fuse setting (unblown state).
Power-on-reset (POR)
Development Part:
It first reads the Laser-fuse HAB_TYPE as 0001 to confirm it is a Development Part and BOOT[3:0] is 0000, indicating USB/UART bootstrap.
Chapter 11 Bootstrap Mode Operation
The bootstrap program is a small program which resides in the internal ROM of i.MX21.
1. For HAB Enable type of silicon, it downloads authenticated binary image code to memory so as to execute in run time or perform Flash update.
2. For HAB Disable type of silicon, it downloads binary image code to memory as to execute in run time or perform Flash update.
The Configuration for USB is for Control Endpoint 0 with Max Packet Size equal 8 byte. Bulk IN at Endpoint 2 with Max Packet Size equal 64 bytes, Bulk OUT at Endpoint 1 with Max Packet Size equal 64 bytes.
Table 21-1. RTIC Signal Descriptions
Hreset： Master Hardware Reset—Active-low asynchronous hardware reset. This signal must always be asserted with HARD_ASYNC_RESET.